A probe card assembly typically includes a contactor substrate carrying a large number of die pad contacting pins, a space transformer for connecting the closely positioned pins to a set of terminals positioned outwardly from the pin positions, and an interface board that serves as a means for connecting the hundreds or thousands of connector terminals to corresponding power, ground and signal terminals of an Automatic Test Equipment (ATE).
The space transformer and the interface board are typically fabricated using well known printed circuit board (PCB) processes and materials. Such components are usually made by adhering a layer of copper over a substrate, sometimes on both sides, then removing unwanted copper (e.g., by etching) after applying a temporary mask, leaving only the desired copper traces. A plurality of such boards are then laminated together and the traces formed thereon are interconnected to provide a means for connecting power and signals to a plurality of micro-miniature electronic devices. Some of these PCB assemblies are made by adding traces to a bare substrate (or a substrate with a very thin layer of copper) usually by a complex process of multiple electroplating steps or by using inkjet printing techniques.
Another application of multilayer circuit boards of the type to be described herein is to provide an improved package interface or external interface device that can be used to improve, augment or even replace the Ball Grid Array (BGA) which has heretofore provided a solution to the problem of packaging and interconnecting an integrated circuit with many hundreds of pins. As pin grid arrays and dual-in-line surface mount (SOIC) packages are produced with more and more pins, and with decreasing spacing between the pins, interfacing difficulties arise in connecting the integrated circuits to systems using the circuit device. For example, as even modern package pins get closer together, the danger of accidentally bridging adjacent pins with solder increases. BGAs have provided an element of solution to the problem in that they enable the solder to be factory-applied to the package in exactly the right amount. Moreover, the shorter an electrical conductor between IC device and the system to which it is connected, the lower its inductance, a property which causes unwanted distortion of signals in high-speed electronic circuits. BGAs, with their very short distance between the package and the PCB, have low inductances and therefore have far superior electrical performance to leaded devices. However, as IC devices continue to include more and more I/Os it is not always convenient to use the standard I/O locations of even BGA packages for connecting an electronic device to a system using the device. There is thus a need for an improved circuit board type of interface means for allowing freedom from connection constraints when high pin-out devices are to be connected to a user system.
There are basically three common “subtractive” methods (methods that remove copper) used in the production of printed circuit boards:
1) Silk screen printing, which uses etch-resistant inks to protect the copper foil, with subsequent etching used to remove the unwanted copper. Alternatively, the ink may be conductive and printed on a blank (non-conductive) board;
2) Photoengraving, which uses a photomask and chemical etching to remove the copper foil from the substrate. The photomask is usually prepared with a photoplotter from data produced by a technician using CAM (computer-aided manufacturing) software. Laser-printed transparencies are typically employed for phototools; however, direct laser imaging techniques are being employed to replace phototools for high-resolution requirements. However, state of the art laser technology can not be utilized to produce trace spacings of less than about 25 microns; and
3) PCB milling, which uses a two or three-axis mechanical milling system to mill away the copper foil from the substrate.
“Additive” processes may also be used. The most common is the “semi-additive” process in which an un-patterned board is provided with a thin layer of copper on its surface. A reverse mask is then applied that, unlike a subtractive process mask, exposes those parts of the substrate that will eventually become the traces. Additional copper is then plated onto the board in the unmasked areas. Tin-lead or other surface platings are then applied. The mask is stripped away and a brief etching step removes the now-exposed original copper laminate from the board, isolating the individual traces. The additive process is commonly used for multi-layer boards as it facilitates the plating-through of the holes (vias) in the circuit board. However, a problem with use of this method for small trace geometries is that the etching step undercuts the edges of the traces yielding undesirable results.
As circuit device geometries have continued to shrink and the number of circuit devices on each die has increased, the number of contact pads per die has also dramatically increased. This, coupled with a decrease in die size, has dramatically increased the pad density of IC devices produced on a processed wafer. Furthermore, with increases in wafer size and decreases in die size and contact pad pitch, the number of dies as well as the number of contact pads on a wafer has likewise increased.
Moreover, since production efficiencies require that all die now be tested at the wafer level, it is no longer feasible to test each die individually, and accordingly, it is important that many die be simultaneously tested. This of course means that thousands of electrically conductive lines must be routed between the probe pins used to contact the die pads (or solder bumps or the like) and a test equipment. In order to accomplish this task by making electrical contact with the die pads, it is necessary to provide thousands of conductive traces on or in the various devices used to link the contacting pins to the ATE. Thus, multilayer PCBs are used to provide the large number of circuit traces in the space available. Compactness of the traces also requires that the trace width and thickness be reduced, as well as the spacing between traces. A typical prior art multi-layer circuit board is shown in FIG. 1.
However, since signals carried by the signal traces are often at very high frequencies, the traces must be electrically isolated from each other in order to avoid cross talk between the traces and to control the impedance of the traces. Stripline technology is commonly used in making multilayer circuit boards.
A stripline is a conductor sandwiched by dielectric between a pair of groundplanes. In practice, a stripline is usually made by etching circuitry from a thin film deposited on one surface of a substrate that has a ground plane formed on the opposite face, then adding a second substrate (which is metalized on only one surface) on top to achieve the second ground plane. Stripline is most often a “soft-board” technology, but using low-temperature co-fired ceramics (LTCC), ceramic stripline circuits are also possible.
All kinds of circuits can be fabricated if a third layer of dielectric is added along with a second interior metal layer, for example, a stack-up of 31 mil Duroid, then 5 mil Duroid, then 31 mil Duroid (Duroid is a trademark of the Rogers Corporation). Transmission lines on either of the interior metal layers behave very nearly like “classic” stripline, the slight asymmetry is not a problem. For example, excellent “broadside” couplers can be made by running transmission lines parallel to each other on the two surfaces. Other variants of the stripline are offset strip line and suspended air stripline (SAS).
For stripline and offset stripline, because all of the fields are constrained to the same dielectric, the effective dielectric constant is equal to the relative dielectric constant of the chosen dielectric material.
Stripline is a TEM (transverse electromagnetic) transmission line media, like coax. This means that it is non-dispersive, and has no cutoff frequency. Stripline filters and couplers always offer better bandwidth than their counterparts in microstrip.
Another advantage of stripline is that excellent isolation between adjacent traces can be achieved (as opposed to microstrip). Very good isolation results when a picket-fence of vias surrounds each transmission line, spaced at less than ¼ wavelength. Stripline can also be used to route RF signals across each other quite easily when offset stripline is used.
Disadvantages of stripline are two: first, it is much harder (and more expensive) to fabricate than microstrip. Lumped-element and active components either have to be buried between the groundplanes (generally a tricky proposition), or transitions to microstrip must be employed as needed to make connections on the top of the board.
A second disadvantage of stripline is that because of the second groundplane, the strip widths are much narrower for a given impedance (such as 50 ohms) and board thickness than for microstrip. This disadvantage is however a benefit as will be described below in the description of the present invention.
A simplified equation for the line impedance of a stripline is given as:
      Z    0    =            60                        ɛ          r                      ⁢          ln      [                        4          ⁢          H                          0.67          ⁢          π          ⁢                                          ⁢                      W            ⁡                          (                              0.8                +                                  t                  D                                            )                                          ]      where the variables are illustrated in FIG. 2 of the drawing.
With these prior art conditions and considerations in mind, it would appear that making devices of the type described with smaller and smaller trace widths and spacings could be accommodated using modern photolithographic processes. However, as suggested by the above equation, for a particular conductor thickness, a decrease in conductor width will result in a proportional increase in conductor impedance. It will thus be appreciated that as trace width reductions are required to allow for increased trace density, a practical limit will be reached based on the material thickness that is to be used in the trace forming process. Although photo-lithographic technology can be used to make very closely spaced thin metal traces having very narrow transverse widths, the use of etching processes on relatively thick conductive layers results in trace undercutting which not only reduces the effective width of the trace but increases the separation between adjacent traces. There is thus a need for a different approach to trace formation; i.e., one that allows the formation of traces in which the transverse height-to-width ratio of the trace cross section is equal to or greater than 1.
It is thus an objective of the present invention to provide a novel multilayer printed circuit board device and method of producing same wherein current carrying traces having optimized cross sectional area enable extremely close arrays of narrow traces to be utilized in applications requiring particular impedance characteristics.
Another objective of the present invention is to provide a circuit board having extremely narrow traces that are closely spaced apart but have large enough cross sectional area to handle a required level of electrical current.
Still another objective of the present invention is to provide a novel process for making circuit board devices with conductive traces having a height-to-width ratio of 1 or greater thus enabling the use of stripline concepts in circuit devices of the types wherein very closely spaced extremely narrow conductive traces are required.